In a processor memory system, a single memory controller typically controls the transmission of data to and from multiple memory modules. In a write transaction, control and address information specifying which location within a memory module will be written to are sent to the memory module followed or accompanied by the actual data to be written. On the other hand, a read transaction can be divided into two sub-transactions. In the first sub-transaction, control and address information are sent from the memory controller to the memory modules. In the second sub-transaction, the read-data is subsequently returned to the memory controller from the addressed memory module. The term “transaction” refers to one device requesting another device to perform a certain operation. The control, address, and data are encoded in electrical signals that are transmitted over wires. However, a common problem associated with the above described transactions and in nearly all long wire communications across a circuit board is maintaining the integrity of the electrical signals. The distortion imposed by typical wire-based transport media on an electrical signal can sufficiently reduce the integrity of the electrical signal resulting in the electrical signal being misinterpreted at the destination devices.
As the feature size of integrated circuit processes shrink, the electrical signal integrity problem worsens. In addition, electrical signal integrity issues seriously impede efforts to achieve high data transfer rates and memory capacity. Electrical signal integrity degrades both with increased signaling speed and with an increased number of receivers, such as increased signal fan-out. In order to increase memory capacity, for example, one can either increase the storage capacity of the individual memory modules or increase the number of memory modules attached to each memory controller. Increasing the number of memory modules increases fan-out which compromises electrical signal integrity. Increasing the storage capacity of an individual memory module can be accomplished by increasing the number of ranks, banks, or the size of the individual memory arrays. All of these options, however, introduce a new host of problems such as increased power consumption, increased management overhead, and increased access latency. An optical bus may be an attractive alternative to electrical busses because optical signals suffer from significantly less loss and distortion over longer distances than do electrical signals.
FIG. 1 shows a schematic representation of a typical optical bus system 100 for transmitting information from a memory controller 101 to one of four memory modules 102-105 using optical signals 106-110. The optical signals 106-110 can be transmitted in free space or waveguides, such as optical fibers. In particular, the memory controller 101 produces an optical clock signal 106 and optical address, control, and data signals 107-110. Partially reflective mirrors divert portions of optical signals 106-110 to corresponding optoelectronic converters which are electronically coupled to the memory modules 102-105. For example, five optoelectronic converters 111-115 are electronically coupled to the memory module 103, and partially reflective mirrors 121-125 divert a portion of each of the optical signals 106-108 to the corresponding optoelectronic converters 111-115. Each of the optoelectronic converters converts the diverted optical signal into an electrical signal encoding the same information as the optical signal. As shown in FIG. 1, even though only one of the memory modules is the target of the transaction, the transaction comprises broadcasting the same optical signals 106-110 to all of the memory modules 102-105. Although optical power increases only slightly with the length of the optical waveguides, the optical power needed to broadcast an optical signal to all of the memory modules is directly proportional to the number of memory modules. In other words, the memory controller 101 must produce enough optical power so that optical signal can be received by all of the memory modules 102-105. Broadcasting control, address, and data to all of the memory modules 102-105 per transaction where only one of the memory modules is the target of the transaction is an inefficient use of optical transport media.
Engineers and computer scientists have recognized a need for methods and systems that can reduce the amount of optical power needed to transmit data encoded in optical signals between transmitting and receiving devices.